Digital ASIC Design Engineer — RTL, SystemVerilog

A leading technology firm in Ottawa is seeking a Digital ASIC Design Engineer to contribute to innovative product designs for high-speed connectivity solutions. This role involves collaboration on functional blocks with responsibilities in code creation, debugging, and lab validation. Candidates should have a degree in electrical or computer engineering, proficiency in System Verilog, and a team-oriented approach. The position offers an annual salary range of CAD 109,000 - CAD 174,000 alongside a comprehensive benefits package.
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