DRAM IP Layout Engineer — Precise Analog Layout & Verification

Micron Technology seeks a DRAM Layout Engineer in Tlaquepaque, Mexico. In this role, you will design and develop IP layouts for DRAM products, ensuring compliance with specifications. The ideal candidate has knowledge in analog layout design within CMOS processes and experience with Cadence tools like Virtuoso and Mentor Calibre. Responsibilities include layout verification and documentation. This full-time position provides a collaborative work environment across global teams.
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