Job Description
Join to apply for the Design Verification role at W3Global
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Must: System Verilog & UVM
Base pay range
CA$60.00/hr - CA$70.00/hr
Description
- DV engineer with 3+-13 yrs of experience.
- Verification of display IP used in graphics card.
- IP/SS and end‑to‑end testing for these blocks.
- Experience in DV flow including SV and UVM.
Seniority level
- Mid-Senior level
Employment type
- Contract
Job function
- Information Technology
- Staffing and Recruiting
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