Job Description
Become a Memory Layout Design Lead with Infosys based in Burnaby, BC. Drive exceptional memory layout solutions in collaboration with circuit design engineers.
The ideal candidate will have at least 5 years of experience in Compiler/Custom Memory Layout design. You will implement advanced memory architectures while leading the layout library design from inception to integration. Your expertise in optimizing layouts for performance will directly contribute to the success of our projects.
Key Responsibilities:
• Develop optimized memory layout designs
• Collaborate with circuit engineers to refine layouts
• Design memory leafcell libraries from ground up
• Validate designs using advanced verification tools
• Address DRC, LVS, and ERC condition standards
Requirements:
• Bachelor’s degree or equivalent IT experience
• 5+ years of relevant experience in memory layout
• Strong knowledge of Finfet technologies
• Exposure to 3nm and 5nm technologies
• Mus...
The ideal candidate will have at least 5 years of experience in Compiler/Custom Memory Layout design. You will implement advanced memory architectures while leading the layout library design from inception to integration. Your expertise in optimizing layouts for performance will directly contribute to the success of our projects.
Key Responsibilities:
• Develop optimized memory layout designs
• Collaborate with circuit engineers to refine layouts
• Design memory leafcell libraries from ground up
• Validate designs using advanced verification tools
• Address DRC, LVS, and ERC condition standards
Requirements:
• Bachelor’s degree or equivalent IT experience
• 5+ years of relevant experience in memory layout
• Strong knowledge of Finfet technologies
• Exposure to 3nm and 5nm technologies
• Mus...