Job Description
Join Synopsys as a Verification Engineer focused on UVM and SystemVerilog. Contribute to cutting-edge memory interface IP by developing robust verification environments and collaborative test cases.
As a key team member, you will drive testing and verification efforts in a dynamic and innovative environment. Your expertise in designing detailed test plans and ensuring comprehensive functional coverage will enhance product reliability. Collaborate with architecture and implementation teams to elevate verification methodologies through technical reviews.
Key Responsibilities:
• Develop detailed verification test plans for memory interface IP
• Implement scalable UVM testbench infrastructure
• Collaborate on technical reviews with architecture teams
• Diagnose complex verification challenges using advanced tools
• Research emerging technologies to enhance verification
Requirements:
• Proficient in SystemVerilog and UVM with hands-on experience
• Strong backgr...
As a key team member, you will drive testing and verification efforts in a dynamic and innovative environment. Your expertise in designing detailed test plans and ensuring comprehensive functional coverage will enhance product reliability. Collaborate with architecture and implementation teams to elevate verification methodologies through technical reviews.
Key Responsibilities:
• Develop detailed verification test plans for memory interface IP
• Implement scalable UVM testbench infrastructure
• Collaborate on technical reviews with architecture teams
• Diagnose complex verification challenges using advanced tools
• Research emerging technologies to enhance verification
Requirements:
• Proficient in SystemVerilog and UVM with hands-on experience
• Strong backgr...